As CMOS nears the end of the projected scaling roadmap, significant efforthas been devoted to the search for new materials and devices that can realizememory and logic. Spintronics, is one of the promising directions for thePost-CMOS era. While the potential of spintronic memories is relatively wellknown, realizing logic remains an open and critical challenge. All Spin Logic(ASL) is a recently proposed logic style that realizes Boolean logic usingspin-transfer-torque (STT) devices based on the principle of non-local spintorque. ASL has advantages such as density, non-volatility, and low operatingvoltage. However, it also suffers from drawbacks such as low speed and staticpower dissipation. Recent work has shown that, in the context of simplearithmetic circuits (adders, multipliers), the efficiency of ASL can be greatlyimproved using techniques that utilize its unique characteristics. Anevaluation of ASL across a broad range of circuits, considering the knownoptimization techniques, is an important next step in determining itsviability. In this work, we propose a systematic methodology for the synthesisof ASL circuits. Our methodology performs various optimizations that benefitASL, such as intra-cycle power gating, stacking of ASL nanomagnets, andfine-grained logic pipelining. We utilize the proposed methodology to evaluatethe suitability of ASL implementations for a wide range of benchmarks viz.random combinational and sequential logic, digital signal processing circuits,and the Leon SPARC3 general-purpose processor. Based on our evaluation, weidentify (i) the large current requirement of nanomagnets at fast switchingspeeds, (ii) the static power dissipation in the all-metallic devices, and(iii) the short spin flip length in interconnects as key bottlenecks that limitthe competitiveness of ASL.
展开▼
